Description
The JM4GDDR2-8K consists of 2pcs 2GB DDR2 SDRAM module. The 2GB module is a 256M x 64bits DDR2-800 Unbuffered DIMM. The 2GB module consists of 16pcs 128Mx8bits DDR2 SDRAMs in 68 ball FBGA packages and a 2048 bits serial EEPROM on a 240-pin printed circuit board. The 2GB module is a Dual In-Line Memory Module and is intended for mounting into 240-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operation frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
Features
-Posted CAS.
-Programmable CAS Latency: 3,4,5.
-Programmable Additive Latency :0, 1,2,3 and 4.
-Write Latency (WL) = Read Latency (RL)-1.
-Burst Length: 4,8(Interleave/nibble sequential).
-Programmable sequential / Interleave Burst Mode.
-Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature).
-Off-Chip Driver (OCD) Impedance Adjustment.
-MRS cycle with address key programs.
-On Die Termination.
-Serial presence detect with EEPROM.

